500-V n-channel insulated-gate bipolar transistor with a trench gate structure
500-V n-channel insulated-gate bipolar transistor with a trench gate structure
复制标题
具有沟槽栅极结构的 500V n 沟道绝缘栅双极晶体管
DOI：
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发表时间：
1989
期刊：
影响因子：
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通讯作者：
B. Baliga
中科院分区：
文献类型：
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作者：
H. Chang;B. Baliga
介绍了一种改进的绝缘栅双极晶体管（IGBT），它具有沟槽栅结构，在200 A/cm/sup 2/的正向导通电流密度下，其正向压降为1.2 V。这种器件结构是使用自对准工艺制造的，该工艺允许具有6 μ m单元的紧密间隔的垂直沟槽栅极。这使得沟道密度增加了五倍，并消除了寄生JFET效应，从而显著降低了正向压降。在UMOS IGBT中获得了2700 A/cm/sup 2/的静态闭锁电流密度。二维计算机模拟的UMOS-IGBT已被执行，以确定最佳的单元设计。这种优化设计预计将增加SOA的电流密度的2.9倍，超过国家的最先进的DMOS-IGBT。>
An improved insulated-gate bipolar transistor (IGBT) with a trench gate structure that demonstrates a low forward voltage drop of 1.2 V at a forward conduction current density of 200 A/cm/sup 2/ is described. This device structure was fabricated using a self-aligned process that permits closely spaced vertical trench gates with a unit cell of 6 mu m. This allows for a fivefold increase of channel density and elimination of the parasitic JFET effect, thus reducing the forward voltage drop significantly. A static latching current density of 2700 A/cm/sup 2/ has been achieved in the UMOS-IGBT. Two-dimensional computer simulations of the UMOS-IGBT have been performed to identify the optimal cell design. This optimal design is predicted to increase the SOA current density by a factor of 2.9 over the state-of-the-art DMOS-IGBT. >