An analogue SIMD focal-plane processor array
An analogue SIMD focal-plane processor array
复制标题
模拟 SIMD 焦平面处理器阵列
DOI：
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发表时间：
2001
期刊：
影响因子：
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通讯作者：
P. Hicks
中科院分区：
文献类型：
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作者：
P. Dudek;P. Hicks
提出了一种用于灰度图像焦平面处理的新型智能传感器VLSI电路。该架构基于细粒度软件可编程SIMD阵列。集成在成像器的每个像素内的处理元件利用开关电流模拟微处理器概念来实现。在0.6 /spl mu/m CMOS工艺中，单元尺寸等于98.6 /spl mu/m/spl乘以/98.6 /spl mu/m。原型21/spl times/21阵列芯片执行超过1.1 GIPS（每秒千兆指令），同时功耗低于40 mW，并在各种早期视觉任务上表现出实时性能。
A new smart-sensor VLSI circuit intended for focal-plane processing of grey-scale images is presented. The architecture is based on a fine-grain software-programmable SIMD array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analogue microprocessor concept. In a 0.6 /spl mu/m CMOS process the cell size is equal to 98.6 /spl mu/m/spl times/98.6 /spl mu/m. A prototype 21/spl times/21 array chip executes over 1.1 GIPS (Giga Instructions Per Second) while dissipating below 40 mW of power and demonstrates a real-time performance on a variety of early vision tasks.