An Analog Front End ASIC for Cardiac Electrical Impedance Tomography
An Analog Front End ASIC for Cardiac Electrical Impedance Tomography
复制标题
DOI：
10.1109/tbcas.2018.2834412
复制
发表时间：
2018-08-01
影响因子：
5.1
通讯作者：
Odame, Kofi
中科院分区：
文献类型：
--
作者：
Rao, Arun;Teng, Yueh-Ching;Odame, Kofi
本文介绍了一种用于心脏电阻抗断层成像系统读出通道的端到端CMOS专用集成电路（ASIC）。该ASIC包括一个用于电流注入的集成电流驱动器、一个仪表放大器、模拟前端用于从电极读取电压的可变增益放大器以及一个带串行外设接口的片上10位逐次逼近寄存器模数转换器。该ASIC是在CMOS 0.18 μ m工艺与3.3 V的电源电压的幅度和相位提取的电压是在数字域中进行匹配滤波器。演示了用于多电极系统的完全集成的解决方案。ASIC中的读出链在500 Hz-700 kHz的频率范围内实现了71 dB的最小信噪比，同时保持了99.7%的平均精度。对于32电极系统，每秒21帧的帧速率是可行的，并且ASIC具有11.8mW的总功耗。
In this paper, an end-to-end CMOS application specific integrated circuit (ASIC) for readout channel in a cardiac electrical impedance tomography system is presented. The ASIC consists of an integrated current driver for current injection, an instrumentation amplifier, variable gain amplifier at the analog front end for voltage readout from electrodes, and an on-chip 10-bit successive approximation register analog to digital converter with serial peripheral interface. The ASIC is fabricated in the CMOS 0.18 mu m process with a supply voltage of 3.3 V. Amplitude and phase extraction of the voltages is performed in the digital domain with a matched filter. A fully integrated solution for use in multiple electrode system is demonstrated. The readout chain in the ASIC achieves a minimum signal-to-noise ratio of 71 dB over the frequency range of 500 Hz-700 kHz, while maintaining an average accuracy of 99.7%. Frame rates of 21 frames per second for a 32 electrode system is feasible, and the ASIC has an overall power consumption of 11.8 mW.