Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems
Phase-Locked Loop Noise Reduction via Phase Detector Implementation for Single-Phase Systems
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DOI：
10.1109/tie.2010.2069070
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发表时间：
2011
影响因子：
7.7
通讯作者：
T. Thacker;D. Boroyevich;R. Burgos;Fei Wang
中科院分区：
文献类型：
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作者：
T. Thacker;D. Boroyevich;R. Burgos;Fei Wang
并网变换器的一个关键部件是锁相环控制子系统，它跟踪电网电压的频率和相角。因此，需要用于控制和保护目的的精确快速响应锁相环来提供这些测量。本文提出了一种基于估计相角的单相锁相环鉴相器反馈机制。出现在估计频率上的纹波噪声，最常见的是锁相条件下的二次谐波，在不使用低通滤波器的情况下被减少或消除，这可能导致延迟的发生，并限制了锁相环响应系统动态变化的整体性能。该方法具有完全消除噪声纹波的能力，并且在极端线畸变条件下，可以将纹波减少至少一半。通过频率反馈实现的其他修改可以将锁相环的稳定时间减少50%。通过对仿真和实验结果的数学分析，验证了所提方法的有效性。
A crucial component of grid-connected converters is the phase-locked loop (PLL) control subsystem that tracks the grid voltage's frequency and phase angle. Therefore, accurate fast-responding PLLs for control and protection purposes are required to provide these measurements. This paper proposes a novel feedback mechanism for single-phase PLL phase detectors using the estimated phase angle. Ripple noise appearing in the estimated frequency, most commonly the second harmonic under phase-lock conditions, is reduced or eliminated without the use of low-pass filters, which can cause delays to occur and limits the overall performance of the PLL response to dynamic changes in the system. The proposed method has the capability to eliminate the noise ripple entirely and, under extreme line distortion conditions, can reduce the ripple by at least half. Other modifications implemented through frequency feedback are shown to decrease the settling time of the PLL up to 50%. Mathematical analyses with the simulated and experimental results are provided to confirm the validity of the proposed methods.