BurstZ: a bandwidth-efficient scientific computing accelerator platform for large-scale data
BurstZ: a bandwidth-efficient scientific computing accelerator platform for large-scale data
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DOI：
10.1145/3392717.3392746
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发表时间：
2020-06
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通讯作者：
Gongjin Sun;Seongyoung Kang;S. Jun
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作者：
Gongjin Sun;Seongyoung Kang;S. Jun
我们提出了BurstZ，一个用于科学计算的带宽高效的加速器平台。虽然GPU和FPGA等加速器提供了巨大的计算能力，但一旦工作集大于板载内存容量，它们的效率就会迅速下降，导致性能受到主机和加速器之间通信带宽的影响。压缩在解决这个问题方面并不是很有用，因为很难有效地压缩浮点数，而浮点数通常由科学数据组成。大多数压缩算法要么对浮点数无效，要么有很高的性能开销。BurstZ是一个基于FPGA的加速器平台，它通过一种新的硬件优化浮点压缩算法（我们称之为sZFP）来解决带宽问题。我们证明，BurstZ可以完全消除加速器的通信瓶颈，使用3D模板代码加速器上实现的原型BurstZ实现。与相同架构的模板代码加速器的手动优化实现进行评估，我们的BurstZ原型的性能比没有压缩的加速器高出近4倍，甚至比具有足够内存的加速器高出2倍以上。BurstZ大大提高了通信效率，我们的原型甚至能够超过具有理想内存访问特性的优化模板核心的上限预测性能，超过2倍。
We present BurstZ, a bandwidth-efficient accelerator platform for scientific computing. While accelerators such as GPUs and FPGAs provide enormous computing capabilities, their effectiveness quickly deteriorates once the working set becomes larger than the on-board memory capacity, causing the performance to become bottlenecked either by the communication bandwidth between the host and the accelerator. Compression has not been very useful in solving this issue due to the difficulty of efficiently compressing floating point numbers, which scientific data often consists of. Most compression algorithms are either ineffective with floating point numbers, or has a high performance overhead. BurstZ is an FPGA-based accelerator platform which addresses the bandwidth issue via a novel hardware-optimized floating point compression algorithm, which we call sZFP. We demonstrate that BurstZ can completely remove the communication bottleneck for accelerators, using a 3D stencil-code accelerator implemented on a prototype BurstZ implementation. Evaluated against hand-optimized implementations of stencil code accelerators of the same architecture, our BurstZ prototype outperformed an accelerator without compression by almost 4X, and even an accelerator with enough memory for the entire dataset by over 2X. BurstZ improved communication efficiency so much, our prototype was even able to outperform the upper limit projected performance of an optimized stencil core with ideal memory access characteristics, by over 2X.