Design and synthesis of low power weighted random pattern generator considering peak power reduction

Design and synthesis of low power weighted random pattern generator considering peak power reduction
复制标题

考虑峰值功率降低的低功率加权随机模式发生器的设计与综合

DOI:
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发表时间:
1999
期刊:
Proceedings (IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems)
影响因子:
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通讯作者:
K. Roy
K. Roy
中科院分区:
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文献类型:
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作者:
Xiaodong Zhang;K. Roy

文献摘要

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为了满足功率和可靠性约束,在测试期间降低平均功率和峰值功率是重要的。在本文中,我们提出了一个低功耗自动测试模式发生器(LPATPG),它可以用于在线测试的大型电路,要求低功耗。LPATPG可以通过具有适当的外部加权逻辑的线性元胞自动机(CA)来实现。当通过在主输入处找到最佳信号活动(信号切换的概率)来降低平均功率时,通过在CA小区中找到最佳初始条件来降低峰值功率。ISCAS基准电路的结果表明,平均功率降低高达79.7%,峰值功率降低高达39.2%,能量降低高达84.4%(与线性元胞自动机相比),同时实现高故障覆盖率。
In order to meet the power and reliability constraints, it is important to reduce average power and peak power during test. In this paper we propose a Low Power Automatic Test Pattern Generator (LPATPG), which can be used during online testing of large circuits requiring low power dissipation. The LPATPG can be implemented by linear cellular automata (CA) with appropriate external weighting logic. While the average power is reduced by finding the optimal signal activities (probabilities of signal switching) at the primary inputs, the peak power is reduced by finding the best initial conditions in the CA cells. Results on ISCAS benchmark circuits show that average power reduction of up to 79.7%, peak power reduction of up to 39.2% and energy reduction of up to 84.4% can be achieved (compared to linear cellular automata) while achieving high fault coverage.