SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol
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SERAD：使用捆绑数据协议的软错误弹性异步设计
DOI：
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发表时间：
2020
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通讯作者：
P. Beerel
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作者：
Sai Aparna Aketi;Smriti Gupta;Huimei Cheng;Joycee Mekie;P. Beerel
对于试图构建能够应对恶劣环境的系统的工程师来说，辐射导致的软错误风险仍然是一个重大挑战。通过设计进行辐射加固（RHBD）的建筑系统是优选的方法，但是现有技术在性能、功率和/或面积方面是昂贵的。本文介绍了一种新的软错误弹性异步并行数据设计模板，SERAD，它使用时间和空间冗余的组合，以减轻单事件瞬变（SET）和翻转（SEU）。SERAD使用错误检测逻辑（EDL）来检测时序元件输入端的SET，并通过重新采样进行纠正。由于SERAD仅在SET存在时支付延迟代价（很少发生），因此其平均性能与基线同步设计相当。我们使用Spice和Verilog仿真相结合的方法测试了SERAD设计，并使用NCSU 45 nm单元库评估了其对开放内核MIPS类处理器的面积、频率和功耗的影响。我们的综合后的结果表明，SERAD设计消耗的面积不到三模冗余（TMR）的一半，表现出显着低于毛刺滤波（GF）的性能下降，并消耗不超过基线未硬化设计的总功率。
The risk of soft errors due to radiation continues to be a significant challenge for engineers trying to build systems that can handle harsh environments. Building systems that are Radiation Hardened by Design (RHBD) is the preferred approach, but existing techniques are expensive in terms of performance, power, and/or area. This paper introduces a novel soft-error resilient asynchronous bundled-data design template, SERAD, which uses a combination of temporal and spatial redundancy to mitigate Single Event Transients (SETs) and upsets (SEUs). SERAD uses Error Detecting Logic (EDL) to detect SETs at the inputs of sequential elements and correct them via re-sampling. Because SERAD only pays the delay penalty in the presence of an SET, which rarely occurs, its average performance is comparable to the baseline synchronous design. We tested the SERAD design using a combination of Spice and Verilog simulations and evaluated its impact on area, frequency, and power on an open-core MIPS-like processor using a NCSU 45nm cell library. Our post-synthesis results show that the SERAD design consumes less than half of the area of the Triple Modular Redundancy (TMR), exhibits significantly less performance degradation than Glitch Filtering (GF), and consumes no more total power than the baseline unhardened design.