Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)
Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable)
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DOI：
10.1109/vts.2019.8758652
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发表时间：
2019-04
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通讯作者：
Soowang Park;S. Gupta
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文献类型：
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作者：
Soowang Park;S. Gupta
现代sram由于缺陷和变化而具有高故障率，特别是在低功率模式下的低压操作期间。在高故障率的情况下，直接应用备用行和列方法会产生很高的开销。由于最近的一篇论文[1]说纠错码（ECC）是高故障率下唯一具有成本效益的方法，我们分析了ECC的优势。这表明，在高开销情况下，ECC提供了一个关键优势：能够纠正不同行中不同位置的单元中的故障。为了找到一个低开销的解决方案，我们转向了分隔字线/位线（DWL+DBL）[2]方法，这是一种基于备件的方法，旨在提供这种功能。由于DWL+DBL也有很高的开销，我们开发了简化ECC和DWL+DBL的想法，并派生了我们的新方法，称为可切换备用列（SSC），其中备用列可以以较低的开销替换不同行中不同位置的故障单元。为了进一步减少开销，我们提出了SSC- disable，它结合了SSC和缓存块禁用[3]。然后，我们开发了一种方法来寻找具有SSC或SSC- disable的全局高效缓存设计。该方法在用户指定的延迟和电力开销约束下，最大限度地提高了单位面积产量（YPA）。我们表明，与最先进的基于ecc的方法相比，提出的SSC-Disable方法显着提高了产量。
Modern SRAMs have high failure rates due to defects and variations, especially during low-voltage operation in low power modes. At high failure rates, a direct application of spare rows and columns approaches incurs high overheads. Since a recent paper [1] says that error correcting codes (ECCs) are the only cost-effective approach under high failure rates, we analyzed the strengths of ECC. This showed that, at high overheads, ECC provides one key advantage: the ability to correct failures in cells in different locations in different rows. To find a low overhead solution, we turn to the Divided Wordline/Bitline (DWL+DBL) [2] approach, a spares-based approach designed to provide exactly this capability. Since DWL+DBL also has high overheads, we develop our ideas for simplifying ECC as well as DWL+DBL and derive our new approach called Switchable Spare Columns (SSC), where a spare column can replace failing cells in different locations in different rows at lower overheads. To further reduce overheads, we propose SSC-Disable, which combines SSC with cache block disabling [3]. We then develop a method to find globally efficient cache designs with SSC or SSC-Disable. This method maximizes yield-per-area (YPA) under user-specified constraints on delay and power overheads. We show that the proposed SSC-Disable approach significantly improves yield compared to state-of-the-art ECC-based approaches.