A monolithic, constant-fraction discriminator using distributed R-C delay line shaping
A monolithic, constant-fraction discriminator using distributed R-C delay line shaping
复制标题
使用分布式 R-C 延迟线整形的单片恒分数鉴别器
DOI：
10.1109/nssmic.1995.504229
复制
发表时间：
1995
期刊：
影响因子：
--
通讯作者：
M. Xu
中科院分区：
文献类型：
--
作者：
M. L. Simpson;G. Young;R. G. Jackson;M. Xu
设计并制作了一个单片CMOS恒比CMOS（constant-fractionalCMOS）晶体管，采用1.2-/spl mu/N阱工艺。该电路采用片上分布式RC延迟线实现恒比整形。延迟线由在接地的第二多晶硅层上的4.8-/spl mu/宽、500-/spl mu/长的多晶硅蛇形层构成。该线路对5 ns上升时间信号产生约1.1 ns延迟，斜率衰减仅为15%。CFD还具有用于解除保险和过零鉴别器的直流反馈，以消除由偏移引起的定时误差。整个电路，包括延迟线，需要200 /spl mu//spl乘以/950 /spl mu/的面积。在-20 mV至-2 V的动态范围内，5 ns上升时间信号的时序游走小于/spl plusmn/150 ps。CFD的每个通道采用5 V单电源供电，功耗为/spl sim/15 mW。
A monolithic, CMOS, constant-fraction discriminator (CFD) was designed and fabricated in a 1.2-/spl mu/ N-well process. This circuit uses an on-chip, distributed R-C delay line to realize the constant-fraction shaping. The delay line is constructed of a 4.8-/spl mu/ wide, 500-/spl mu/ long serpentine layer of polysilicon above a grounded second layer of polysilicon. This line generates about 1.1 ns of delay for a 5-ns risetime signal with a slope degradation of only 15%. The CFD also features DC feedback for both the arming and zero-crossing discriminators to eliminate timing errors caused by offsets. The entire circuit, including the delay line, requires an area of 200 /spl mu//spl times/950 /spl mu/. The timing walk for 5-ns risetime signals over the dynamic range from -20 mV to -2 V was less than /spl plusmn/150 ps. Each channel of the CFD consumed /spl sim/15 mW from a single 5-V supply.