Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES
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设计具有信息流强制的安全加密加速器:AES 案例研究

DOI:
10.1145/3316781.3317798
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发表时间:
2019
期刊:
The 56th Annual Design Automation Conference (DAC
影响因子:
--
通讯作者:
Zhang, Zhiru
Zhang, Zhiru
中科院分区:
--
文献类型:
--
作者:
Jiang, Zhenghong;Jin, Hanchen;Suh, G. Edward;Zhang, Zhiru

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设计安全的加密加速器具有挑战性,因为设计决策和实现缺陷可能会产生漏洞。为了提供高安全性保证,我们建议设计和构建具有硬件级信息流控制的加密加速器,从而可以正式验证实现的安全性。本文以AES加速器为例,演示了如何将加密加速器的安全需求表示为安全执行的信息流策略。我们在FPGA上的AES原型表明,所提出的保护对面积和性能的影响很小。
Designing a secure cryptographic accelerator is challenging as vulnerabilities may arise from design decisions and implementation flaws. To provide high security assurance, we propose to design and build cryptographic accelerators with hardware-level information flow control so that the security of an implementation can be formally verified. This paper uses an AES accelerator as a case study to demonstrate how to express security requirements of a cryptographic accelerator as information flow policies for security enforcement. Our AES prototype on an FPGA shows that the proposed protection has a marginal impact on area and performance.
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影响因子: --
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