20.1 A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
20.1 A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv-step
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20.1 A 5GS/s 7.2 ENOB 基于 VCO 的时间交错 ADC 实现 30.5fJ/转换步
DOI：
10.1109/isscc.2019.8662412
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
W. Dehaene
中科院分区：
文献类型：
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作者：
Maarten Baert;W. Dehaene
技术缩放在速度和功耗方面对数字电路都非常有益。然而，传统的模拟技术受到不断降低的电源电压的挑战。高度数字化的基于VCO的ADC能够直接从改进的数字性能中受益[1];然而，基于VCO的最先进设计的分辨率和采样速率对于大多数应用来说是不够的。提出了一种基于改进的高速低功耗环形振荡器和异步计数策略的更快、更高效的VCO ADC架构。该架构采用8倍时间交错，并结合片内校准。该设计采用28 nm CMOS工艺实现，在5GS/s下，在奈奎斯特附近SNDR（7.2 ENOB）为45.2dB，功耗仅为22.7mW，瓦尔登FOM为30.5fJ/conv-step。核心面积仅为0.023mm 2。这些结果表明，基于VCO的ADC是下一代以太网和高速无线通信的可行选择。
Technology scaling has been very beneficial for digital circuits both in terms of speed and power. Traditional analog techniques however are challenged by the ever-decreasing supply voltages. Highly digital VCO-based ADCs are able to benefit directly from improved digital performance [1]; however, the resolution and sampling rate of state-of-the-art VCO-based designs are insufficient for most applications. This paper presents a faster and more efficient VCO-based ADC architecture based on an improved high-speed, low-power ring oscillator and an asynchronous counting strategy. The architecture is 8× time-interleaved and combined with on-chip calibration. The design is implemented in 28nm CMOS and achieves 45.2dB SNDR (7.2 ENOB) near Nyquist at 5GS/s while consuming only 22.7mW, resulting in a Walden FOM of 30.5fJ/conv-step. The core area is only 0.023mm 2. These results demonstrate that VCO-based ADCs are a viable choice for next-generation Ethernet and high-speed wireless communication.