Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches

Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches
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具有使用页眉和页脚电源开关的电源门控单元架构的超低压保持 SRAM

DOI:
10.1109/ojcas.2021.3104945
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发表时间:
2021
影响因子:
2.6
通讯作者:
Sugahara Satoshi
Sugahara Satoshi
中科院分区:
--
文献类型:
--
作者:
Yoshida Hayato;Shiotsu Yusaku;Kitagata Daiki;Yamamoto Shuu'ichirou;Sugahara Satoshi

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研究了一种用于功率门控(PG)应用的采用页眉和页脚功率开关(HFP)的超低电压保持SRAM(ULVR-SRAM)单元。该单元可以根据由HFPS控制的单元电压(Vcell)来改变其工作模式:当施加普通电源电压时,该单元可以充当高性能SRAM单元。当Vcell被降低到超低电压时,单元可以转变到ULVR模式,并且在不丢失其数据的情况下显著降低泄漏功率,即可以使用ULVR来实现实质性的PG。通过引入仅在ULVR模式期间自动感应的体偏压来增强降低漏电功率的能力。该设计方法基于准静态噪声容限,其中确定了晶体管尺寸和Vcell的偏置条件,以便在ULVR模式下保持足够高的噪声容限的同时最小化泄漏功率。优化设计的超低功耗静态随机存储器单元表现出了良好的PG能力:使用超低功耗可降低~98%的漏电功率,在8KB宏下可实现最小1.5μ的盈亏平衡时间S。ULVR-SRAM可以提供一种新的节能PG结构。
An ultralow-voltage retention SRAM (ULVR-SRAM) cell using header and footer power-switches (HFPSs) is investigated for power-gating (PG) applications. The cell can change its operational mode depending on the cell voltage ( Vcell) controlled by the HFPSs: When the ordinary supply voltage is applied, the cell can act as a high-performance SRAM cell. When Vcellis reduced to an ultralow voltage, the cell can transition to the ULVR mode and dramatically reduce the leakage power without losing its data, i.e., the substantive PG can be achieved using the ULVR. The ability of leakage power reduction is enhanced by introducing the body biases that are automatically induced only during the ULVR mode. The design methodology is developed based on quasi-static noise margins, where the transistor sizes and the bias condition for Vcellare determined so as to minimize the leakage power with keeping a sufficiently high noise margin in the ULVR mode. An optimally designed ULVR-SRAM cell shows excellent PG ability: The leakage power can be reduced by ~98% using the ULVR and a minimally short break-even time of 1.5μs can be achieved for the 8KB macro. The ULVR-SRAM can provide a new class of energy efficient PG architecture.