Van der Waals Heterostructure Engineering for Ultralow-Resistance Contact in 2D Semiconductor P-Type Transistors
Van der Waals Heterostructure Engineering for Ultralow-Resistance Contact in 2D Semiconductor P-Type Transistors
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DOI：
10.1007/s11664-024-10920-5
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发表时间：
2024-01
影响因子：
2.1
通讯作者：
Ning Yang;Ting-Hao Hsu;Hung-Yu Chen;Jian Zhao;Hongming Zhang;Han Wang;Jing Guo
中科院分区：
文献类型：
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作者：
Ning Yang;Ting-Hao Hsu;Hung-Yu Chen;Jian Zhao;Hongming Zhang;Han Wang;Jing Guo
实现低电阻接触对于开发基于二维（2D）材料的场效应晶体管（FET）至关重要。虽然已经研究了2D半导体的n型接触，但是对2D半导体的p型接触的理解和设计仍然非常有限。在这项研究中，我们提出并计算探索了三种策略，以改善p型2D FET的接触电阻，这仍然是2D逻辑技术的关键瓶颈，通过货车德瓦尔斯（vdW）材料异质结构的工程：（i）在高功函数金属和2D半导体之间插入石墨烯层，其可导致高功函数金属与WSe 2半导体之间的石墨烯插层接触的约60 Ω μm的低接触电阻;（ii）设计vdW金属和2D半导体之间的原子堆叠顺序，这可以导致约50 Ω μm的接触电阻;（iii）将2D分层半导体从两侧夹在vdW金属之间，这可以进一步将情况（i）和（ii）的接触电阻分别降低至~ 47 Ω μm和~ 36 Ω μm。实验制造和表征说明了接触的结构工程的可行性。上述结构设计可以导致显著降低的金属诱导间隙态（MIGS）和低的空穴势垒高度，从而导致低接触电阻。它们也自然地与栅极全包围（GAA）晶体管结构兼容。除了接触材料的选择，vdW结构设计提供了实现低接触电阻的顶型2D FET的替代方法。
Achieving a low resistance contact is essential for developing two-dimensional (2D) material-based field-effect transistors (FETs). While n-type contacts to 2D semiconductors have been studied, understanding and designs forp-type contacts to 2D semiconductors remain very limited. In this study, we propose and computationally explore three strategies to improve the contact resistance inp-type 2D FETs, which remains a critical bottleneck of 2D logic technology, through the engineering of van der Waals (vdW) material heterostructures: (i) intercalating a graphene layer between a high-work-function metal and 2D semiconductor, which can result in low contact resistance of ~ 60 Ω μm for the graphene-intercalated contact between a high-work-function metal and WSe2semiconductor; (ii) engineering the atomic stacking order between a vdW metal and 2D semiconductor, which can result in contact resistance of ~ 50 Ω μm; (iii) sandwiching the 2D layered semiconductor between vdW metals from both sides, which can further reduce the contact resistance to ~ 47 Ω μm and ~ 36 Ω μm for cases (i) and (ii), respectively. Experimental fabrication and characterization illustrate the feasibility of structural engineering of contacts. The above structural designs can lead to significantly reduced metal-induced gap states (MIGS) and low barrier height for holes, resulting in low contact resistance. They are also naturally compatible with the gate-all-around (GAA) transistor structure. In addition to contact materials selection, vdW structural design offers an alternative approach for achieving low contact resistance top-type 2D FETs.