A 12-bit intrinsic accuracy high-speed CMOS DAC
A 12-bit intrinsic accuracy high-speed CMOS DAC
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DOI：
10.1109/4.735536
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发表时间：
1998-12
期刊：
影响因子：
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通讯作者：
José Bastos;A. Marques;M. Steyaert;W. Sansen
中科院分区：
文献类型：
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作者：
José Bastos;A. Marques;M. Steyaert;W. Sansen
介绍了一种采用0.5/SPLµ/m标准数字工艺集成的12位固有精度数模(D/A)转换器。它基于电流转向双分段6+2+4架构，不需要校准、不修剪或动态平均。微分非线性(DNL)和积分非线性(INL)分别为0.3和0.6最低有效位(LSB‘s)。测得的毛刺能量为1.9 pV.s。对于12位分辨率，转换器的更新速率达到300MS/S。通过将锁存器的电源电压降低到2.0V，毛刺能量被降低到亚pV.s，而对于8位分辨率，更新速率达到500MS/S。最糟糕的情况是功耗为320 mW，它由一个3.3V的电压供电。芯片面积为3.2 mm/sup 2/。
A 12-bit intrinsic accuracy digital-to-analog (D/A) converter integrated in a standard digital 0.5 /spl mu/m CMOS technology is presented. It is based on a current steering doubly segmented 6+2+4 architecture and requires no calibration, no trimming, or dynamic averaging. The differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 and 0.6 least significant bits (LSB's), respectively. The measured glitch energy is 1.9 pV.s. For a 12-bit resolution, the converter reaches an update rate of 300 MS/s. By reducing the voltage supply of the latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and the update rate reaches 500 MS/s, for a resolution of 8 bits. The worst case power consumption is 320 mW, and it operates from a single 3.3 V voltage supply. The die area is 3.2 mm/sup 2/.