Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms
复制标题
应用模型和多抽象片上网络平台的联合验证
DOI：
10.4018/jertcs.2010103005
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
F. Moraes
中科院分区：
文献类型：
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作者：
Sanna Määttä;Leandro Möller;L. Indrusiak;Luciano Ost;M. Glesner;J. Nurmi;F. Moraes
在片上MPSOC的多处理器系统的设计期间，通常会忽略应用模型。这是由于难以捕获应用程序限制并将其应用于平台的设计空间探索。在本文中，我们提出了一种应用程序建模形式主义，该形式主义支持应用程序和平台模型的联合验证。为了支持设计师在准确性，可观察性和验证速度之间进行权衡分析，我们表明这种方法可以在多个抽象级别上处理平台模型的连续完善。对单个应用程序的联合验证的案例研究连续映射到三种不同的平台模型上，证明了所提出的方法的适用性。
Application models are often disregarded during the design of multiprocessor Systems-on-Chip MPSoC. This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.