A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
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DOI：
10.1109/jssc.2012.2217874
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发表时间：
2012-12-01
影响因子：
5.4
通讯作者：
Flynn, Michael P.
中科院分区：
文献类型：
--
作者：
Fredenburg, Jeffrey A.;Flynn, Michael P.
虽然电荷再分配逐次逼近（SAR）ADC效率很高，但比较器噪声和其他效应将最高效的工作限制在10-B ENOB以下。本文介绍了一种过采样、噪声整形SAR ADC架构，该架构采用8位B SAR DAC阵列实现10位B有效位。噪声整形方案对比较器噪声和量化噪声进行整形，从而将比较器噪声与ADC性能解耦。环路滤波器由两抽头电荷域FIR滤波器和积分器的级联组成，即使使用低质量积分器也能实现良好的噪声整形。原型ADC采用65 nm CMOS制造，核心面积为0.03 mm（2）。工作在90 MS/s，它消耗806 μ W从1.2 V电源。
Although charge-redistribution successive approximation (SAR) ADCs are highly efficient, comparator noise and other effects limit the most efficient operation to below 10-b ENOB. This work introduces an oversampling, noise-shaping SAR ADC architecture that achieves 10-b ENOB with an 8-b SAR DAC array. A noise-shaping scheme shapes both comparator noise and quantization noise, thereby decoupling comparator noise from ADC performance. The loop filter is comprised of a cascade of a two-tap charge-domain FIR filter and an integrator to achieve good noise shaping even with a low-quality integrator. The prototype ADC is fabricated in 65-nm CMOS and occupies a core area of 0.03 mm(2). Operating at 90MS/s, it consumes 806 mu W from a 1.2-V supply.