Extraction of geometry-related interconnect variation based on parasitic capacitance data
Extraction of geometry-related interconnect variation based on parasitic capacitance data
复制标题
DOI：
10.1109/led.2014.2344173
复制
发表时间：
2014-08
影响因子：
4.9
通讯作者：
Lijie Sun;Jia Cheng;Zheng Ren;Ganbing Shang;ShaoJian Hu;Shoumian Chen;Yu-Hang Zhao;Long Zhang-
中科院分区：
文献类型：
--
作者：
Lijie Sun;Jia Cheng;Zheng Ren;Ganbing Shang;ShaoJian Hu;Shoumian Chen;Yu-Hang Zhao;Long Zhang-
本文提出了一种新的互连寄生提取流程，该流程考虑了与几何相关的变化。42个互连电容负载由55纳米工艺技术制造，并测量以表征几何变化。根据新的提取流程，优化并建立了互连工艺文件（ITF）。结果表明，优化后的ITF明显改善了版图寄生提取工具的提取误差和场求解器的模拟误差。同时，本文设计了一种基于电荷诱导注入无误差电荷电容测量的非重叠信号产生电路的片上互连线测试技术，以简化测试过程。
A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with this optimized ITF. Meanwhile, an on-chip interconnect test technique with nonoverlapping signal generation circuitry based on charge-induced-injection error-free charge-based capacitance measurement has been designed in this letter to simplify the test procedure.