A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm
A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm
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“软”eFPGA 物理设计方法以及 180nm 和 90nm 的案例研究
DOI：
10.1109/isvlsi.2006.1
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
R. Saleh
中科院分区：
文献类型：
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作者：
Victor O. Aken'Ova;R. Saleh
我们最近在嵌入式FPGA方面的工作主要集中在软IP方法上，其中可编程结构在RTL级进行描述，并使用ASIC数字流程和通用标准单元来实现。早期结果显示，在面积、延迟和电力开销方面有显著的损失。然而，在这样的流程中使用战术标准单元和结构化的物理设计方法，我们能够在面积和延误方面获得巨大的节省。我们将这种新方法定义为Soft++eFPGA。本文提供了详细的物理设计流程，特别强调了布局规划、互连规划和时钟树综合。在一组采用180 nm和90 nm工艺实现的实际基准电路上，我们展示了该方法在处理较大电路方面的优势
Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology