Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics
Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics
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漏极偏置对阈值电压波动的影响及其对电路特性的影响
DOI：
10.1109/iedm.2008.4796721
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
M. Hane
中科院分区：
文献类型：
--
作者：
M. Miyamura;T. Nagumo;K. Takeuchi;K. Takeda;M. Hane
通过可寻址晶体管阵列测量和3D Monte-Carlo TCAD仿真，分析了饱和区Vth波动的增强机制。经证实，重掺杂光晕器件中的随机掺杂波动 (RDF) 会增强源漏不对称性，从而导致 DIBL 和饱和 Vth (Vth_sat) 的非高斯分布。测量的 DIBL 行为被精确建模并在统计电路仿真中实现，以评估对 SRAM 稳定性的影响。用于减轻 RDF 的 halo 优化对于实现大幅缩放的 SRAM 单元非常重要。
Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled and implemented in statistical circuit simulation, to evaluate the impact on SRAM stability. Optimization of halo for mitigating RDF is important for achieving aggressively scaled SRAM cells.