A full-custom design flow and a top-down RTL-to-GDS flow for adiabatic quantum-flux-parametron logic using a commercial EDA design suite
A full-custom design flow and a top-down RTL-to-GDS flow for adiabatic quantum-flux-parametron logic using a commercial EDA design suite
复制标题
使用商业 EDA 设计套件的绝热量子通量参数逻辑的全定制设计流程和自上而下的 RTL 到 GDS 流程
DOI：
10.1109/tasc.2023.3261267
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发表时间：
2023
影响因子：
1.8
通讯作者：
Yoshikawa Nobuyuki
中科院分区：
文献类型：
--
作者：
Tanaka Tomoyuki;Ayala Christopher L.;Whiteley Stephen;Mlinar Eric;Barker Aaron;Chen Song;Belov Anton;Barbee Troy;Kawa Jamil;Yoshikawa Nobuyuki
绝热量子通量参变(AQFP)电路是一种超低功耗的超导数字逻辑电路。它的功耗比最先进的CMOS电路低五个数量级，比另一种与之竞争的数字超导技术RSFQ电路低三个数量级。社会需要的计算资源每年都在增加，AQFP电路是下一代计算机的有力候选者。在以前的研究中，设计并实现了一个4位MANA微处理器和一个使用AQFP逻辑的16位Kogge-Stone加法器。这些电路几乎都是手工设计的，需要改进开发环境才能实现AQFP电路的实际应用。因此，我们使用了通常用于CMOS设计的Synopsys EDA工具，创建了用于逻辑单元设计的全定制设计流程和用于自动设计组合逻辑电路的自上而下流程。我们将电路设计编辑器与仿真和验证工具集成在一起，实现了全定制设计流程。对于自上而下的流程，我们创建了一个自动执行逻辑综合、路径平衡、单元布局以及信号和激励布线的环境。已经成功地设计了1024位加法器，具有200多万个约瑟夫森结(JJ)。
The adiabatic quantum-flux-parametron (AQFP) circuit is a superconductor digital logic family with extremely low power consumption. It consumes five orders less power than the state-of-the-art CMOS circuits and three orders of magnitude less power than RSFQ circuits, another competing digital superconductor technology. The computing resources required by society are increasing every year, and the AQFP circuit is a strong candidate for the next generation of computers. In previous research, a 4-bit MANA microprocessor and a 16-bit Kogge-Stone adder using AQFP logic were designed and demonstrated. These circuits were designed almost by hand, and the development environment needs to be improved to implement AQFP circuits for practical applications. So, we used Synopsys EDA tools typically used for CMOS design to create a full-custom design flow for logic cell design and a top-down flow to design combinational logic circuits automatically. We integrated a circuit design editor with simulation and verification tools for the full-custom design flow. For the top-down flow, we created an environment that automatically performs logic synthesis, path balancing, cell placement, and signal and excitation routing. 1024-bit adders with more than two million Josephson junctions (JJs) have been successfully designed.