A novel low temperature integration of hybrid CMOS devices on flexible substrates
A novel low temperature integration of hybrid CMOS devices on flexible substrates
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柔性基板上混合 CMOS 器件的新型低温集成
DOI：
10.1016/j.orgel.2009.06.012
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发表时间：
2009
影响因子：
3.2
通讯作者：
D. Allee
中科院分区：
文献类型：
--
作者：
S. Gowrisanker;M. Quevedo;H. Alshareef;B. Gnade;S. Venugopal;R. Krishna;K. Kaftanoglu;D. Allee
在这项工作中，我们展示了一种新的集成方法来制造CMOS电路的塑料基板（聚萘二甲酸乙二醇酯，PEN）。我们使用并五苯和非晶硅（a-Si：H）薄膜晶体管（TFT）作为p沟道和n沟道器件，分别。n沟道TFT的最高处理温度为180°C，p沟道TFT的最高处理温度为120°C。在这项工作中，CMOS电路包括反相器，NAND和NOR门。CMOS集成工艺流程后nMOS和pMOS的载流子迁移率分别为0.75和0.05 cm 2/Vs。nMOS的阈值电压（Vt）为1.14V，pMOS为−1.89V。CMOS反相器的电压传输曲线显示增益为16。集成灵活的NAND和NOR CMOS门的正确逻辑操作也被证明。此外，我们表明，pMOS栅极电介质可能会失败后，电应力。
In this work we demonstrate a novel integration approach to fabricate CMOS circuits on plastic substrates (poly-ethylene naphthalate, PEN). We use pentacene and amorphous silicon (a-Si:H) thin-film transistors (TFTs) as p-channel and n-channel devices, respectively. The maximum processing temperature for n-channel TFTs is 180°C and 120°C for the p-channel TFTs. CMOS circuits demonstrated in this work include inverters, NAND, and NOR gates. Carrier mobilities for nMOS and pMOS after the CMOS integration process flow are 0.75 and 0.05 cm2/Vs, respectively. Threshold voltages (Vt) are 1.14V for nMOS and −1.89V for pMOS. The voltage transfer curve of the CMOS inverter showed a gain of 16. Correct logic operation of integrated flexible NAND and NOR CMOS gates is also demonstrated. In addition, we show that the pMOS gate dielectric is likely failing after electrical stress.