An ADPLL-Based PSK Receiver for VHBR 13.56-MHz Contactless Smartcards and NFC Applications
An ADPLL-Based PSK Receiver for VHBR 13.56-MHz Contactless Smartcards and NFC Applications
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DOI：
10.1109/tcsii.2017.2763986
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发表时间：
2018-11
期刊：
影响因子：
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通讯作者：
Lei Wang;Chundong Wu;Liang Zhang;Lisong Feng;Juhui Li;Alan Chang;Y. Lian
中科院分区：
文献类型：
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作者：
Lei Wang;Chundong Wu;Liang Zhang;Lisong Feng;Juhui Li;Alan Chang;Y. Lian
本文提出了一种全数字锁相环（ADPLL）作为相移键控（PSK）接收机的非常高的比特率为13.56 MHz的智能卡。给出了从系统级到电路级的详细实现。这种基于ADPLL的PSK解调器主要由一个无脉冲收缩效应的高动态范围时间数字转换器（TDC）、一个双路数字环路滤波器和一个基于电容分频无抖动的高分辨率数控振荡器组成。该设计采用GF CMOS 40 nm工艺制造，核心面积仅为0.035 mm 2。测量结果表明，低电流消耗为40 mA的锁相和70 mA的PSK解调与1.2 V电源。积分非线性和微分非线性的TDC是小于0.6 LSB。该原型可以解调8-PSK的符号率为6.78 MHz，对应的数据速率为20.34 Mb/s，与4.1 pJ/bit的能量效率。
This brief proposes an all-digital phase-locked loop (ADPLL) used as the phase-shift keying (PSK) receiver for a very high bit rate of 13.56-MHz smartcards. A detailed implementation from system to circuit level is presented. This ADPLL-based PSK demodulator mainly consists of a high dynamic range time to digital converter (TDC) without pulse shrinking effect, a dual-path digital loop filter, and a fine resolution digital controlled oscillator based on capacitor division without dithering. This design is fabricated by GF CMOS 40-nm technology with a core area of only 0.035 mm2. The measurement results show low current consumption of 40 mA for phase locking and 70 mA for PSK demodulation with 1.2-V supply. Both integral non-linearity and differential non-linearity of our TDC are smaller than 0.6 LSB. This prototype can demodulate 8-PSK at a symbol rate of 6.78 MHz, corresponding to a data rate of 20.34 Mb/s, with an energy efficiency of 4.1 pJ/bit.