An SVM Approach for Five-Phase Current Source Converters Output Current Harmonics and Common-Mode Voltage Mitigation
An SVM Approach for Five-Phase Current Source Converters Output Current Harmonics and Common-Mode Voltage Mitigation
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DOI:
10.1109/tie.2019.2934055
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发表时间:
2020-07
影响因子:
7.7
通讯作者:
Jinwei He;Yuan Lyu;Junfei Han;Chengshan Wang
中科院分区:
文献类型:
--
作者:
Jinwei He;Yuan Lyu;Junfei Han;Chengshan Wang
In this article, an enhanced five-segment space vector modulation (SVM) approach is proposed for a five-phase current source converter (CSC) to simultaneously reduce its output current harmonics and common-mode voltage (CMV). To realize proper output current harmonics mitigation, the reference current vector is synthesized by adjacent four large vectors and one zero vector in the fundamental plane. At the same time, the dwell times of four adjacent large vectors are calculated to actively control the corresponding current projection in the third sequence plane. In addition, the zero vector is selected according to the ranking of the instantaneous filter capacitor voltage absolute value to reduce the peak CMV. Comparing to voltage source converter (VSC) counterparts where the CMV is not affected by the ac output voltage and current harmonic components, it is interesting to find that the CMV enveloping of the CSC has a strong connection with its third harmonic output current. Then, a sequence arrangement for the five-segment SVM approach is proposed to ensure only one switch action during vector states transition. Finally, a transformerlike loss model is established to evaluate the loss performance of the CSC with a different modulation approach and a vector sequence selection method.