A pipelined A/D conversion technique with near-inherent monotonicity
A pipelined A/D conversion technique with near-inherent monotonicity
复制标题
具有近乎固有单调性的流水线 A/D 转换技术
DOI：
10.1109/82.401178
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
Hae
中科院分区：
文献类型：
--
作者：
P. Yu;Hae
提出了一种简单的流水线A/D转换技术，它提供了比传统流水线转换器更优越的上级单调性。该技术涉及反馈电容器的简单重新布置。与现有技术不同，它不会增加电路复杂性，增加功耗或牺牲转换速度。相反，该技术允许针对给定的差分线性度目标使用较小的电容器，从而在保持速度的同时降低功耗。该技术适用于每级具有宽范围位的流水线结构，包括1-B/级。Monte Carlo模拟表明，在3-/spl sigma/电平下，0.781%的电容失配与1.56%的满量程比较器误差相结合，在2-B/级架构中提供了超过95.2%的12-B成品率。>
A simple pipelined A/D conversion technique, which provides superior monotonicity to that of conventional pipelined converters is presented. The technique involves simple re-arrangement of the feedback capacitor. Unlike existing techniques, it does not add circuit complexity, increase power consumption, or sacrifice conversion speed. On the contrary, the technique allows the use of smaller capacitors for a given differential linearity target, thereby reducing the power consumption while maintaining the speed. The technique is applicable to pipelined architectures with a wide range of bits per stage including 1-b/stage. Monte Carlo simulation indicates that at 3-/spl sigma/ levels, 0.781% capacitor mismatch combined with 1.56%-of-full-scale comparator errors provides over 95.2% 12-b yield in a 2-b/stage architecture. >