An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC
An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC
复制标题
异构 MPSoC 功耗感知设计的高效框架
DOI：
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发表时间：
2013
影响因子：
12.3
通讯作者：
Dominique Blouin
中科院分区：
文献类型：
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作者：
R. B. Atitallah;E. Senn;D. Chillet;Mickael Lanoe;Dominique Blouin
目前，设计低功耗的复杂嵌入式系统是许多电子领域企业面临的主要挑战。有多种动机促使设计人员考虑低功耗设计，例如延长寿命，提高电池寿命，限制电池容量和温度约束。不幸的是，缺乏有效的方法和准确的工具来获得不同抽象级别的完整系统的功率/能量估计。提出了一种异构多处理器片上系统（MPSoC）功耗/能量估计和优化的全局框架。在此框架下，定义了一种功耗建模方法，并开发了一个开放的平台。我们的方法考虑到所有嵌入式系统相关的方面;软件，硬件和操作系统。该平台代表开放电力和能源优化平台和评估（Open-PEOPLE）。它包括各种各样的评估工具，以涵盖整个设计流程。从功能评估到真实的电路板测量，我们的平台可帮助设计人员开发新的功耗模型，探索新的架构，并应用优化技术，以降低系统的能耗和功耗。建议的功率估计框架的有用性和有效性证明了通过一个典型的嵌入式系统的设想围绕Xilinx Virtex II Pro FPGA平台。
Currently, designing low-power complex embedded systems is a main challenge for corporations in a large number of electronic domains. There are multiple motivations which lead designers to consider low-power design such as increasing lifetime, improving battery longevity, limited battery capacity, and temperature constraints. Unfortunately, there is a lack of efficient methodology and accurate tool to obtain power/energy estimation of a complete system at different abstraction levels. This paper presents a global framework for power/energy estimation and optimization of heterogeneous multiprocessor system-on-chip (MPSoC). Within this framework, a power modeling methodology is defined, and an open platform is developed. Our methodology takes into account all the embedded system relevant aspects; the software, the hardware, and the operating system. The platform stands for Open Power and Energy Optimization PLatform and Estimator (Open-PEOPLE). It includes diverse estimation tools with respect to their abstraction levels in order to cover the overall design flow. Starting from functional estimation and down to real boards measurements, our platform helps designers to develop new power models, to explore new architectures, and to apply optimization techniques in order to reduce energy and power consumption of the system. The usefulness and the effectiveness of the proposed power estimation framework is demonstrated through a typical embedded system conceived around the Xilinx Virtex II Pro FPGA platform.