Layout-Based Test Coverage Verification for High-Reliability Devices
Layout-Based Test Coverage Verification for High-Reliability Devices
复制标题
高可靠性器件基于布局的测试覆盖率验证
DOI：
10.1109/tsm.2017.2746089
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发表时间：
2017
影响因子：
2.7
通讯作者：
Kazuhiko Iwasaki
中科院分区：
文献类型：
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作者：
Yoshikazu Nagamura;Kenji Shiozawa;Toru Koyama;Jun Matsushima;Kazuhiko Tomonaga;Yutaka Hoshi;Shuji Nomura;Masayuki Arai;Kazuhiko Iwasaki
测试质量是消除测试逃逸和实现高可靠性大规模集成（LSI）器件的关键。本文提出了一个新的概念，称为“物理测试覆盖率”，以验证测试覆盖率的基础上的物理布局的大规模集成电路。物理测试覆盖率计算为器件中所有导线的临界面积与LSI测试未检测到的导线的临界面积之间的比率。从未检测到的导线的临界区域和生产线的缺陷密度，测试逃逸的风险可以预测。为了有效地开发可以最小化测试图案数量的LSI测试，未检测到的导线按照与每条导线相关的关键区域进行优先级排序。即使当传统的“逻辑”测试覆盖率足够高，以满足覆盖率标准，本文中研究的一些LSI器件表现出低的物理测试覆盖率取决于LSI电路的物理布局。物理覆盖的概念被应用到一些LSI产品的测试开发中，测试质量得到了大幅提高，器件测试逃逸率达到90%。
Test quality is critical to eliminate test escapes and to achieve high-reliability large-scale integrated (LSI) devices. This paper proposes a new concept called “physical test coverage” to verify test coverage based on the physical layout of LSI circuits. The physical test coverage is calculated as the ratio between the critical area of all wires in a device and that of wires undetected by LSI tests. From the critical area of undetected wires and the defect density of a manufacturing line, the risk of test escapes can be predicted. To effectively develop LSI tests that can minimize the number of test patterns, undetected wires are prioritized by the critical area related to each wire. Even when the conventional “logical” test coverage is high enough to satisfy the coverage criterion, some LSI devices investigated in this paper showed low physical test coverage depending on the physical layout of the LSI circuit. The concept of physical coverage was applied in the test development of some LSI products, and the test quality was substantially improved, such that 90% of test escapes of a device were eliminated.