A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme
A 0.7V single-supply SRAM with 0.495um2 cell in 65nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme
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0.7V 单电源 SRAM，采用 65nm 技术，采用 0.495um2 单元，采用自写回读出放大器和级联位线方案
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
T. Yabe
中科院分区：
文献类型：
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作者：
K. Kushida;A. Suzuki;G. Fukano;A. Kawasumi;O. Hirabayashi;Y. Takeyama;T. Sasaki;A. Katayama;Y. Fujimura;T. Yabe
提出了一种在低电源电压运行时具有高密度单元的新型 SRAM 架构。自回写读出放大器在 0.6V 电压下实现单元故障率提高两个数量级以上。级联位线方案节省了分层位线层的额外工艺成本。具有 256 kb SRAM 的测试芯片采用 65 nm CMOS 技术中的 0.495 um2 单元，演示了 0.7 V 单电源运行。
A novel SRAM architecture with a high density cell in low supply voltage operation is proposed. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 um2 cell in 65 nm CMOS technology demonstrated 0.7 V single supply operation.