Microarchitecture and performance analysis of a SPARC-V9 microprocessor for enterprise server systems
Microarchitecture and performance analysis of a SPARC-V9 microprocessor for enterprise server systems
复制标题
用于企业服务器系统的 SPARC-V9 微处理器的微架构和性能分析
DOI：
10.1109/hpca.2003.1183533
复制
发表时间：
2003
期刊：
影响因子：
--
通讯作者：
Yasunori Kimura
中科院分区：
文献类型：
--
作者：
M. Sakamoto;A. Katsuno;Aiichiro Inoue;Takeo Asakawa;H. Ueno;Kuniki Morita;Yasunori Kimura
我们开发了一款1.3 GHz SPARC-V9处理器：SPARC 64 V。该处理器旨在满足企业服务器和高性能计算的要求。多用户交互工作负载下的处理速度对系统平衡非常敏感，因为其中包含大量的内存请求。根据多年的大型机系统开发经验，我们重视设计一个平衡的通信结构。为了完成这项任务，系统级性能研究必须尽早开始。因此，我们开发了一个性能模型，其中包括一个详细的处理器模型和详细的内存模型，在硬件设计开始之前。我们不断更新它。一旦逻辑模拟器可用，我们就用它来验证性能模型，以提高其准确性。该模型非常有效地使我们能够实现性能目标并快速完成开发。本文介绍了SPARC 64 V的微结构和性能分析，为硬件设计提供了依据。
We developed a 1.3-GHz SPARC-V9 processor: the SPARC64 V. This processor is designed to address requirements for enterprise servers and high-performance computing. Processing speed under multiuser interactive workloads is very sensitive to system balance because of the large number of memory requests included. From many years of experience with such workloads in mainframe system developments, we give importance to design a well-balanced communication structure. To accomplish this task, a system-level performance study must begin at an early please. Therefore we developed a performance model, which consists of a detailed processor model and detailed memory model, before hardware design was started. We updated it continuously. Once a logic simulator became available, we used it to verify the performance model for improving its accuracy. The model quite effectively enabled us to achieve performance goals and finish development quickly. This paper describes the SPARC64 V microarchitecture and performance analyses for hardware design.