PolySA: Polyhedral-Based Systolic Array Auto-Compilation
PolySA: Polyhedral-Based Systolic Array Auto-Compilation
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DOI：
10.1145/3240765.3240838
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发表时间：
2018-11
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影响因子：
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通讯作者：
J. Cong;Jie Wang
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作者：
J. Cong;Jie Wang
由于需要缩短手动设计漫长的开发周期，自动脉动阵列生成长期以来一直是一个有趣的话题。现有的自动脉动阵列生成方法从算法构建依赖图，并将图中的计算节点迭代映射到带有时间戳的处理单元（PE）中，时间戳指定了在PE内操作的节点顺序。有许多先前的工作实现了这一想法并为专用集成电路（ASIC）生成了设计。然而，所有这些工作都依赖人工干预，并且与手动设计相比，通常生成的设计较差。在这项工作中，我们介绍我们正在进行的名为PolySA的编译框架，它利用多面体模型的强大功能在现场可编程门阵列（FPGA）上实现脉动阵列架构的端到端编译。PolySA是第一个利用高级综合的最新进展在FPGA上生成高性能脉动阵列架构的全自动编译框架。我们在两个关键应用——矩阵乘法和卷积神经网络上展示了PolySA。PolySA能够在一小时内生成最优设计，其性能与最先进的手动设计相当。
Automatic systolic array generation has long been an interesting topic due to the need to reduce the lengthy development cycles of manual designs. Existing automatic systolic array generation approach builds dependency graphs from algorithms, and iteratively maps computation nodes in the graph into processing elements (PEs) with time stamps that specify the sequences of nodes that operate within the PE. There are a number of previous works that implemented the idea and generated designs for ASICs. However, all of these works relied on human intervention and usually generated inferior designs compared to manual designs. In this work, we present our ongoing compilation framework named PolySA which leverages the power of the polyhedral model to achieve the end-to-end compilation for systolic array architecture on FPGAs. PolySA is the first fully automated compilation framework for generating high-performance systolic array architectures on the FPGA leveraging recent advances in high-level synthesis. We demonstrate PolySA on two key applications–matrix multiplication and convolutional neural network. PolySA is able to generate optimal designs within one hour with performance comparable to state-of-the-art manual designs.