Hybrid integration of VCSEL's to CMOS integrated circuits
Hybrid integration of VCSEL's to CMOS integrated circuits
复制标题
VCSEL 与 CMOS 集成电路的混合集成
DOI：
10.1109/2944.778285
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发表时间：
1999
影响因子：
4.9
通讯作者：
C. Wilmsen
中科院分区：
文献类型：
--
作者：
R. Pu;C. Duan;C. Wilmsen
为了确定用于光学互连和自由空间光学加工的垂直腔面发射激光器(VCSEL)智能像素的最佳制备方法，开发并比较了三种垂直腔面发射激光器(VCSEL)与CMOS集成电路芯片的混合集成技术。三种键合技术中的每一种都使用不同的方式将VCSEL连接到集成电路，并将电接触连接到n镜和p镜。所有这三种技术都将衬底从VCSEL晶片上移除，留下一个单独的VCSEL阵列与单独的像素结合。键合VCSEL的4/SPL倍/4和/或8/SPL倍/8阵列产生非键合VCSEL的典型电学和光学特性。阈值电压低至1.5V，动态电阻低至30个/SPL欧米茄/，表明获得了良好的电接触。对于孔径为20微米/米的垂直腔面发射激光器和孔径为6微米/米的垂直腔面发射激光器，观察到的光功率分别为/SPL sim/10 mW和0.7 mW。VCSEL工作在200Mb/S(我们的设备限制)，光输出的上升和下降时间<；1 ns。
Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4/spl times/4 and/or 8/spl times/8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 /spl Omega/ were measured, indicating good electrical contact was obtained. Optical power as high as /spl sim/10 mW for a VCSEL with a 20-/spl mu/m aperture and 0.7 mW with a 6-/spl mu/m aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS.