SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
SCAFFI: An intrachip FPGA asynchronous interface based on hard macros
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SCAFFI：基于硬宏的片内FPGA异步接口
DOI：
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发表时间：
2007
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通讯作者：
Ney Laert Vilar Calazans
中科院分区：
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作者：
Julian J. H. Pontes;R. Soares;Ewerson Carvalho;F. Moraes;Ney Laert Vilar Calazans
随着电路几何结构的发展，构建完全同步的 VLSI 电路变得越来越不可行。然而，在 VLSI 设计中采用纯异步策略之前，应该采用全局异步局部同步 (GALS) 设计方法。使用复杂的现场可编程组件（例如最先进的 FPGA）进行电路设计也遵循同样的趋势。在 GALS 设计中，关键的一步是定义同步区域之间的异步接口。本文提出了 SCAFFI，一种用于互连 FPGA 内部模块的新型异步接口。该接口基于时钟拉伸技术以避免亚稳态。与其他接口不同的是，它可以使用两个逻辑级别进行扩展，并且不需要使用仲裁器。此外，通过使用专用 FPGA 硬宏，还增强了实现的紧凑性。 RSA 加密核心的 GALS 版本实现演示了 SCAFFI 的使用。
Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globally asynchronous, locally synchronous (GALS) design approaches should take over. The design of circuits using complex field programmable components like state of the art FPGAs follows this same trend. In GALS design, a critical step is the definition of asynchronous interfaces between synchronous regions. This paper proposes SCAFFI, a new asynchronous interface to interconnect modules inside FPGAs. The interface is based on clock stretching techniques to avoid metastability. Differently from other interfaces, it can use both logic levels for stretching and do not require the use of arbiters. Also, compactness of the implementation is enhanced by the use of dedicated FPGA hard macros. A GALS version implementation of an RSA cryptography core demonstrates the use of SCAFFI.