Floorplanning and topology generation for application-specific Network-on-Chip
Floorplanning and topology generation for application-specific Network-on-Chip
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DOI：
10.1109/aspdac.2010.5419825
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发表时间：
2010-01
期刊：
影响因子：
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通讯作者：
Bei Yu;Sheqin Dong;Song Chen;S. Goto
中科院分区：
文献类型：
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作者：
Bei Yu;Sheqin Dong;Song Chen;S. Goto
片上网络（NoC）架构被认为是传统的基于总线的通信架构的一个有前途的替代方案。在本文中，我们提出了一个两阶段框架来解决特定应用的noc拓扑生成问题。在楼面规划阶段，我们进行分区驱动的楼面规划。在平面规划后阶段，采用启发式方法和最小成本最大流量算法插入交换机和网络接口。最后，我们分配路径以最小化功耗。实验结果表明，该算法具有较好的节能效果。
Network-on-Chip(NoC) architectures have been proposed as a promising alternative to classical bus-based communication architectures. In this paper, we propose a two phases framework to solve application-specific NoCs topology generation problem. At floorplanning phase, we carry out partition driven floorplanning. At post-floorplanning phase, a heuristic method and a min-cost max-flow algorithm is used to insert switches and network interfaces. Finally, we allocate paths to minimize power consumption. The experimental results show our algorithm is effective for power saving.