Impact of FPGA Architecture on Area and Performance of CGRA Overlays
Impact of FPGA Architecture on Area and Performance of CGRA Overlays
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FPGA 架构对 CGRA 覆盖面积和性能的影响
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
J. Anderson
中科院分区：
文献类型：
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作者：
Ian Taras;J. Anderson
粗粒度可重构阵列（CGRA）是一种可编程逻辑器件，具有可编程处理单元和数据通路互连。CGRA可以实现为定制ASIC或在FPGA上实现为覆盖层。CGRA的一个关键要素是它们通常是具有快速编译时间的软件可编程的-这是由其粗粒度特性产生的优势，简化了CAD映射任务。我们在两个商用FPGA（Intel和Xilinx）上实现了两个之前发布的CGRA作为覆盖层，并考虑了底层FPGA架构对CGRA面积和性能的影响。我们提出了优化的覆盖，以利用FPGA的架构功能，并显示了1.93倍的峰值性能提高，以及最大面积节省31.1%和48.5%的英特尔和Xilinx，分别相对于一个天真的第一次切割实现。我们还提出了一种新的技术，可配置的多路复用器的实现，它嵌入到SRAM配置的选择信号，节省35.7%的面积。该研究使用开源CGRA-ME（建模和探索）框架进行[1]。
Coarse-grained reconfigurable arrays (CGRAs) are programmable logic devices with ALU-style processing elements and datapath interconnect. CGRAs can be realized as custom ASICs or implemented on FPGAs as overlays . A key element of CGRAs is that they are typically software programmable with rapid compile times – an advantage arising from their coarse-grained characteristics, simplifying CAD mapping tasks. We implement two previously published CGRAs as overlays on two commercial FPGAs (Intel and Xilinx), and consider the impact of the underlying FPGA architecture on the CGRA area and performance. We present optimizations for the overlays to take advantage of the FPGA architectural features and show a peak performance improvement of 1.93x, as well as maximum area savings of 31.1% and 48.5% for Intel and Xilinx, respectively, relative to a naive first-cut implementation. We also present a novel technique for a configurable multiplexer implementation, which embeds the select signals into SRAM configuration, saving 35.7% in area. The research is conducted using the open-source CGRA-ME (modeling and exploration) framework [1].