Carrizo: A High Performance, Energy Efficient 28 nm APU
Carrizo: A High Performance, Energy Efficient 28 nm APU
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Carrizo：高性能、高能效 28 nm APU
DOI：
10.1109/jssc.2015.2464688
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发表时间：
2016
影响因子：
5.4
通讯作者：
Kathryn Wilcox
中科院分区：
文献类型：
--
作者：
B. Munger;David R. Akeson;Srikanth Arekapudi;T. Burd;Harry R. Fair;J. Farrell;Dave Johnson;G. Krishnan;H. McIntyre;E. McLellan;S. Naffziger;Russell Schreiber;Sriram Sundaram;Jonathan White;Kathryn Wilcox
AMD的第六代“ Carrizo” APU针对12-35 W移动计算形式，含有31亿晶体管，占据了250.04 mm 2，并在28 nm HKMG平面双氧化物FET技术中实施了12个金属层与第5代“ Kaveri” APU（也是28 nm的设计）相比与技术缩小的功率相似在处理器核心以及L2高速缓存中的Wordline和位辅助技术中缩放较低的最小电压要求。
AMD's 6th generation “Carrizo” APU, targeted at 12-35 W mobile computing form factors, contains 3.1 billion transistors, occupies 250.04 mm 2 and is implemented in a 28 nm HKMG planar dual-oxide FET technology with 12 metal layers. The design achieves a 29% improvement in transistor density compared to the 5th generation “Kaveri” APU, also a 28 nm design, and implements several power management features resulting in area and power improvements similar to a technology shrink. Increased power density makes meeting the thermal limits required for reliability and power distribution to the APU's processors substantial design challenges. Pre-silicon thermal analysis is used to understand and take advantage of thermal gradients. Adaptive voltage-frequency scaling in the processor core as well as wordline and bitline assist techniques in the L2 cache enable lower minimum voltage requirements.