Memristor-Specific Failures: New Verification Methods and Emerging Test Problems
Memristor-Specific Failures: New Verification Methods and Emerging Test Problems
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DOI：
10.1109/vts52500.2021.9794274
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发表时间：
2022-04
期刊：
影响因子：
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通讯作者：
B. Biswas;S. Gupta
中科院分区：
文献类型：
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作者：
B. Biswas;S. Gupta
我们研究忆阻器比率逻辑 (MRL) 中两种类型的忆阻器特定逻辑故障，忆阻器比率逻辑是一种广泛研究的忆阻器-CMOS 混合逻辑设计风格。先前已观察到级联故障会导致某些 MRL 逻辑电路中的电压显着下降，从而导致逻辑值错误。在这里，我们首次对此类逻辑错误进行系统研究，并将其关键属性确定为电路结构和所应用模式的函数。然后，我们提出了一种生成模式的方法，该模式会导致给定 MRL 电路产生最坏情况的输出电压，从而促进预制验证。然后，我们首次研究了压控忆阻器器件的另一种逻辑故障，即忆阻器串联且极性相同、从 Ron 状态切换到 Roff 状态时的竞争。我们表明，这种竞争可能会导致不确定的行为，具体取决于电路结构、忆阻器参数值以及应用模式时忆阻器的初始状态。然后，我们生成激发此类竞争的模式和初始状态，从而可能导致逻辑错误以启用验证。
We study two types of memristor-specific logic failures in Memristor Ratioed Logic (MRL), an extensively studied Memristor-CMOS hybrid logic design style. Cascading failures have been previously observed as causing significant voltage degradation, and hence logic values errors, in certain MRL logic circuits. Here, we present the first systematic study of this type of logical error and identify its key properties as a function of circuit structure and patterns applied. We then propose a method to generate patterns that cause the worst-case output voltage for a given MRL circuit and hence facilitate pre-fabrication verification. We then present the first study of another type of logic failure for voltage controlled memristor devices, namely a race when memristors in series, and with the same polarity, switch states from Ron to Roff. We show that such a race can cause non-deterministic behavior depending on circuit structure, values of memristor parameters, and the initial states of memristors when a pattern is applied. We then generate patterns and initial states that excite such race and hence potentially cause logic errors to enable verification.