Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes
Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes
复制标题
DOI：
10.1109/ted.2022.3225512
复制
发表时间：
2023-01
影响因子：
3.1
通讯作者：
Zhenlin Pei;M. Mayahinia;Hsiao-Hsuan Liu;M. Tahoori;F. Catthoor;Z. Tokei;C. Pan
中科院分区：
文献类型：
--
作者：
Zhenlin Pei;M. Mayahinia;Hsiao-Hsuan Liu;M. Tahoori;F. Catthoor;Z. Tokei;C. Pan
基于石墨烯的互连被认为是传统铜（Cu）互连的有希望的替代品，因为它们具有良好的电性能。在本文中，开发了一个互连-存储器协同设计框架，以有效地优化各种基于石墨烯的互连技术。本文对四种互连材料和异质设计方案进行了基准测试，以优化大缓存级SRAM在延迟和每次访问能量、能量延迟积（EDP）和能量延迟面积积（EDAP）方面的性能。基于现实的子阵列设计和器件技术，进行了大的设计空间探索。研究了各种互连和阵列级设计参数，以量化基于石墨烯的线的最佳存储性能的真正潜力。
Graphene-based interconnects are considered promising replacements for traditional copper (Cu) interconnect due to their great electric properties. In this article, an interconnect-memory co- design framework is developed to efficiently optimize various graphene-based interconnect technologies. Four interconnect materials and heterogeneous design schemes are benchmarked against their traditional Cu counterparts to optimize large cache-level SRAM performance in terms of delay and energy per access, energy-delay product (EDP), and energy-delay-area product (EDAP). A large design space exploration is performed based on realistic subarray design and device technology. Various interconnect- and array-level design parameters are studied to quantify the true potential of graphene-based wires for optimal memory performance.