A method of fault analysis for test generation and fault diagnosis
A method of fault analysis for test generation and fault diagnosis
复制标题
一种用于测试生成和故障诊断的故障分析方法
DOI：
10.1109/43.3952
复制
发表时间：
1988
期刊：
影响因子：
--
通讯作者：
J. Rajski
中科院分区：
文献类型：
--
作者：
H. Cox;J. Rajski
针对大型组合电路的测试生成和故障诊断，提出了一种故障覆盖率分析方法。使用16值逻辑系统Gemini分两步对输入向量进行分析。执行前向传播以确定网络中的每条线路在网络包含任何单个或多个故障时可以采用的所有可能值的集合。根据在初级输出处观察到的值，执行向后隐含以确定每条线路实际携带的值。一些推导出的值意味着线路没有故障；同样，一些值意味着驱动线路的子网络或线路本身存在故障。通过跟踪此信息，可以将故障定位到其等价类内。采用了一种扩展的故障模型，该模型包括固定故障、固定打开故障和延迟故障。隐含地考虑了所有多重性的多个故障；因此，在存在未测试或不可测试线路的情况下，使用该方法获得的结果不会失效。>；
The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines. >