Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves
Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves
复制标题
学习布局：使用强化学习和定向移动进行 FPGA 布局
DOI：
--
复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Vaughn Betz
中科院分区：
文献类型：
--
作者：
Mohamed A. Elgammal;Kevin E. Murray;Vaughn Betz
模拟退火（SA）被广泛用于FPGA布局中，无论是作为一个独立的算法，还是初始分析布局后的细化步骤。基于SA的砂矿已被证明以长运行时间为代价实现高质量的结果。在本文中，我们提出了一个改进的SA为基础的布局使用定向移动和强化学习（RL）。所提出的定向移动比传统的随机移动更有效地探索解空间，并且针对线长和定时优化。RL代理通过动态选择最有效的移动类型来进一步提高效率。总的来说，这些增强功能允许比传统退火更有效地探索大的解决方案空间。VTR基准测试套件的实验结果表明，我们的技术优于广泛使用的VTR 8放置器在广泛的CPU质量的权衡点，实现了5-11%减少线长和可比或更短的关键路径延迟在给定的运行时间，或33-50%缩短运行时间的目标质量点。
Simulated Annealing (SA) is widely used in FPGA placement either as a standalone algorithm or a refinement step after initial analytical placement. SA-based placers have been shown to achieve high-quality results at the cost of long runtimes. In this paper, we propose an improvement of SA-based placement using directed moves and Reinforcement Learning (RL). The proposed directed moves explore the solution space more efficiently than traditional random moves, and target both wirelength and timing optimizations. The RL agent further improves efficiency by dynamically selecting the most effective move types as optimization progresses. Taken together, these enhancements allow more efficient exploration of the large solution space than traditional annealing. Experimental results on the VTR benchmark suite show that our technique outperforms the widely-used VTR 8 placer across a wide range of CPU-quality trade-off points, achieving 5-11% reduced wirelength and comparable or shorter critical path delays in a given runtime, or 33-50% shorter runtimes for a target quality point.