A novel high-speed sense-amplifier-based flip-flop
A novel high-speed sense-amplifier-based flip-flop
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DOI：
10.1109/tvlsi.2005.859586
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发表时间：
2005-11
影响因子：
2.8
通讯作者：
A. Strollo;D. Caro;E. Napoli;N. Petra
中科院分区：
文献类型：
--
作者：
A. Strollo;D. Caro;E. Napoli;N. Petra
提出了一种新的基于传感放大器的触发器。所提出电路的输出锁存器可以被视为基于标准 NAND 的设置/重置锁存器和 NC-/sup 2/MOS 方法之间的混合解决方案。所提出的触发器提供无比设计、降低的短路功耗和无干扰操作。针对 0.25-/spl mu/m 技术获得的仿真结果表明，相对于最近提出的高速触发器，时钟到输出延迟和功耗有所改善。新电路已成功应用于高速直接数字频率合成器芯片，突出了所提出的触发器在基于高速标准单元的应用中的有效性。
A new sense-amplifier-based flip-flop is presented. The output latch of the proposed circuit can be considered as an hybrid solution between the standard NAND-based set/reset latch and the NC-/sup 2/MOS approach. The proposed flip-flop provides ratioless design, reduced short-circuit power dissipation, and glitch-free operation. The simulation results, obtained for a 0.25-/spl mu/m technology, show improvements in the clock-to-output delay and the power dissipation with respect to the recently proposed high-speed flip-flops. The new circuit has been successfully employed in a high-speed direct digital frequency synthesizer chip, highlighting the effectiveness of the proposed flip-flop in high-speed standard cell-based applications.