FPGA Montgomery multiplier architectures - a comparison
FPGA Montgomery multiplier architectures - a comparison
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FPGA Montgomery 乘法器架构 - 比较
DOI：
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
J. McCanny
中科院分区：
文献类型：
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作者：
C. McIvor;Máire O’Neill;J. McCanny
介绍了SOS，CIO和FIOS Montgomery乘法算法的新型FPGA体系结构。 Xilinx virtex2 Pro FPGA中的18/SPL时间/18位乘数和快速携带的外观逻辑嵌入了FPGA的家族中，用于执行这些算法所需的普通乘法和添加。给出了详细的分析，突出了在硬件中实现这些体系结构的优点和弱点。这表明，CIOS乘数体系结构的整体表现最佳，并且随着单词大小的使用降低，此选项与其他选项之间的性能差距不断增加。此外，SOS乘数优于FIOS乘数用于较大的单词大小，但反之亦然，随着单词大小减小。还表明，可以通过选择特定的单词大小来定制乘数体系结构的效率，时间效率或两者的混合物。
Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented. The 18/spl times/18-bit multipliers and fast carry look-ahead logic embedded within the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions required by these algorithms. A detailed analysis is given, highlighting the advantages and weaknesses of each of these architectures when implemented in hardware. This shows that the CIOS multiplier architectures perform best overall, with the performance gap between this and the other options increasing as the word size used decreases. In addition, the SOS multipliers outperform the FIOS multipliers for larger word sizes, but vice versa as the word size decreases. It is also shown that one can tailor the multiplier architectures to be area efficient, time efficient or a mixture of both, by choosing a particular word size.