The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs
复制标题
编译器优化对 FPGA 高级综合的影响
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
J. Anderson
中科院分区：
文献类型：
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作者：
Qijing Huang;Ruolong Lian;Andrew Canis;Jongsok Choi;R. Xi;S. Brown;J. Anderson
我们考虑编译器优化对高级综合 (HLS) 生成的 FPGA 硬件质量的影响。使用在最先进的 LLVM [1] 编译器中实现的 HLS 工具，我们研究了编译器优化对电路面积、执行周期、Fmax 和挂钟时间等硬件指标的影响。我们评估了 LLVM 中实现的 56 种不同的编译器优化，并表明某些优化会显着影响硬件质量。此外，我们表明硬件质量也受到优化应用顺序的影响。然后，我们提出了一种新的 HLS 导向的编译器优化方法，其中我们在优化过程的间歇点执行部分 HLS 和分析，并使用结果明智地消除预计会损害生成的硬件质量的优化过程的影响。结果表明，与使用标准 -O3 优化级别相比，我们的方法生成的电路平均速度性能提高了 16%。
We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated FPGA hardware. Using a HLS tool implemented within the state-of-the-art LLVM [1] compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, Fmax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality. Moreover, we show that hardware quality is also affected by the order in which optimizations are applied. We then present a new HLS-directed approach to compiler optimizations, wherein we execute partial HLS and profiling at intermittent points in the optimization process and use the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality. Results show that our approach produces circuits with 16% better speed performance, on average, versus using the standard -O3 optimization level.