A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks
A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks
复制标题
10Gb/s 硅光子收发器，具有 150μW 120μs 锁定时间数字监控模拟微环波长稳定性，适用于 1Tb/s/mm2 芯片到芯片光网络
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
C. Baudot
中科院分区：
文献类型：
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作者：
Y. Thonnart;M. Zid;J. L. Jiménez;G. Waltener;R. Polster;O. Dubray;F. Lepin;S. Bernabé;S. Menezo;G. Pares;O. Castany;L. Boutafa;P. Grosse;B. Charbonnier;C. Baudot
硅光子学在过去几年中降低了光学互连的成本并提高了性能，由于微环调制器和滤波器的引入，短距离波分复用（WDM）链路最近出现了[1-5]。然而，在[1]中预见到的片上光网络的前景必须面临可扩展的低占用空间基本驱动程序的集成挑战，以及由于核心在不同负载下自加热而导致的重热应力下的稳健运行。这项工作提出了一种3d堆叠的cmos -on- si光子收发器芯片，其中包括针对多核处理器的模对模WDM光通信的基本构建模块：10Gbps 2.5Vpp OOK调制器驱动程序，相关接收器，以及使用微环加热器的数字监督模拟波长稳定，并在0至90°C的工作范围内重新映射，每个微环的总占地面积为0.01mm2。
Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5Vpp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm2 per microring.