Thermal-aware power network design for IR drop reduction in 3D ICs
Thermal-aware power network design for IR drop reduction in 3D ICs
复制标题
DOI：
10.1109/aspdac.2012.6164995
复制
发表时间：
2012-03
期刊：
影响因子：
--
通讯作者：
Zuowei Li;Yuchun Ma;Qiang Zhou;Yici Cai;Yu Wang;Tingting Huang;Yuan Xie
中科院分区：
文献类型：
--
作者：
Zuowei Li;Yuchun Ma;Qiang Zhou;Yici Cai;Yu Wang;Tingting Huang;Yuan Xie
由于垂直堆叠层上的高度集成，电源/接地网络设计成为3D IC设计中的关键挑战之一。由于漏热依赖性，3D设计中增加的片上温度由于增加的导线电阻和增加的漏电流而对IR压降产生严重影响。电源/接地（P/G）TSV可以通过垂直连接不同层上的片上P/G网络来帮助缓解IR压降违规。然而，大多数先前的工作仅满足PG TSV规划的全部潜力的余量，因为P/G网格被限制在统一的拓扑结构中。此外，忽略电阻变化和漏电流也会使结果不准确。在本文中，我们提出了一个有效的热感知P/G TSV规划算法的基础上的灵敏度模型与温度相关的漏电流考虑。该方法克服了均匀P/G网格拓扑的局限性，通过在非均匀P/G网格中引入短导线连接P/G TSV，充分利用P/G TSV规划对P/G网络进行优化。此外，由于3D IC中的高温引起的电阻变化和漏电流增加，可以获得更准确的结果。理论分析和实验结果都表明了该方法的有效性。结果表明，忽略对功率传输的热影响可以低估IR下降约11%。为了缓解严重的IR下降违规，需要比没有考虑热影响的情况多51.8%的P/G TSV。结果还表明，我们的P/G TSV规划的基础上的灵敏度模型可以减少42.3%的最大IR下降，并减少违反节点的数量82.4%。
Due to the high integration on vertical stacked layers, power/ground network design becomes one of the critical challenges in 3D IC design. With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Power/ground (P/G) TSVs can help to relieve the IR drop violation by vertically connecting the on-chip P/G networks on different layers. However, most previous work only fulfills a margin of the full potential of PG TSVs planning since the P/G grids are restricted in a uniform topology. Besides, the overlook of resistance variation and leakage current will make the results less accurate. In this paper, we present an efficient thermal-aware P/G TSVs planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. The proposed method can overcome the limitation of uniform P/G grid topology and make full use of P/G TSVs planning for the optimization of P/G network by allowing short wires to connect the P/G TSVs to P/G grids in non-uniform topology. Moreover, with resistance variation and increased leakage current caused by high temperature in 3D ICs, more accurate result can be obtained. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3% and reduce the number of violated nodes by 82.4%.