A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments
复制标题
用于故障注入实验的可配置片上毛刺时钟发生器
DOI：
10.1587/transfun.e95.a.263
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
Akashi Satoh
中科院分区：
文献类型：
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作者：
S. Endo;T. Sugawara;N. Homma;T. Aoki;Akashi Satoh
本文提出了一种集成在FPGA中的毛刺时钟发生器，用于评估密码模块的故障注入攻击及其对策。该发生器利用现代FPGA中常见的时钟管理功能，生成具有时间电压尖峰的时钟信号。毛刺时钟周期的形状和时序可在运行时配置。所提出的发生器可以嵌入在单个FPGA中，而无需任何外部仪器（例如，脉冲发生器和可变电源）。这种集成使得能够进行可靠且可再现的故障注入实验。在本文中，我们研究所提出的发电机的特点，通过实验侧信道攻击标准评估委员会（佐世保）。实验结果表明，该方法可以将毛刺的产生时间控制在0.17ns左右。我们还展示了它的应用程序的安全错误攻击对RSA处理器。
This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchy-clock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Side-channel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17ns. We also demonstrate its application to the safe-error attack against an RSA processor.