Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators
Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators
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DOI：
10.1145/3531437.3539715
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发表时间：
2022-06
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影响因子：
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通讯作者：
J. Heo;A. Fayyazi;Amirhossein Esmaili;M. Pedram
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文献类型：
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作者：
J. Heo;A. Fayyazi;Amirhossein Esmaili;M. Pedram
本文介绍了稀疏周期性收缩（SPS）加速器，它是支持轻量级神经网络的最先进的硬件加速器。具体而言，SPS稀疏性实现了一种新的硬件设计方法，该方法通过紧急修剪方案，基于周期性模式的稀疏性（PPS）解锁。通过利用PPS的规律性，我们的稀疏感知编译器优化重新排序的权重，并使用一个简单的索引单元在硬件中创建权重和激活之间的匹配。通过编译器与硬件的协同设计，SPS编译器在避免高索引开销和模型精度损失的同时，享有更高的并行度。在VGG和ResNet等流行的基准测试中进行评估后，SPS Quarterlow和附带的神经网络编译器在针对FPGA器件的卷积神经网络（CNN）加速器设计中的表现优于之前的工作。与其他支持稀疏性的权重存储格式相比，SPS的能效提高了4.49倍，同时将总权重存储（非修剪权重加索引）的存储需求降低了3.67倍，将索引内存的存储需求降低了22，044倍。
This paper introduces the sparse periodic systolic (SPS) dataflow, which advances the state-of-the-art hardware accelerator for supporting lightweight neural networks. Specifically, the SPS dataflow enables a novel hardware design approach unlocked by an emergent pruning scheme, periodic pattern-based sparsity (PPS). By exploiting the regularity of PPS, our sparsity-aware compiler optimally reorders the weights and uses a simple indexing unit in hardware to create matches between the weights and activations. Through the compiler-hardware codesign, SPS dataflow enjoys higher degrees of parallelism while being free of the high indexing overhead and without model accuracy loss. Evaluated on popular benchmarks such as VGG and ResNet, the SPS dataflow and accompanying neural network compiler outperform prior work in convolutional neural network (CNN) accelerator designs targeting FPGA devices. Against other sparsity-supporting weight storage formats, SPS results in 4.49 × energy efficiency gain while lowering storage requirements by 3.67 × for total weight storage (non-pruned weights plus indexing) and 22,044 × for indexing memory.