Degradation in FPGAs
Degradation in FPGAs
复制标题
FPGA 性能退化
DOI：
10.1145/1723112.1723152
复制
发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Stott E
中科院分区：
文献类型：
--
作者：
Stott E
超大规模集成电路技术的进步是通过工艺缩放来增加电路密度，但随着几何尺寸的缩小，可靠性受到越来越大的威胁。FPGA由于其规则的结构和重新配置的能力，在解决降级和故障方面具有独特的地位，使其具有实现系统级可靠性增强的潜力。为了评估挑战的规模，开发了一种测量和监测FPGA退化的方法，并用于对现代设备进行加速寿命测试。这揭示了时序性能的明显、逐渐退化，与负偏置温度不稳定性和热载流子注入（两种最重要的VLSI退化机制）的预期效应相匹配。通过建模，进一步了解了老化现象-显示了典型LUT的退化如何受到不同使用条件的影响，并详细预测了对电路行为的影响。
Progress in VLSI technology is driven by increasing circuit density through process scaling, but with shrinking geometry comes an increasing threat to reliability. FPGAs are uniquely placed to tackle degradation and faults due to their regular structure and ability to reconfigure, giving them the potential to implement system-level reliability enhancements. To assess the scale of the challenge, a method for measuring and monitoring degradation in an FPGA was developed and used to conduct an accelerated life test on a modern device. This revealed a clear, gradual degradation in timing performance that matches the expected effects of Negative-Bias Temperature Instability and Hot Carrier Injection, two of the most important VLSI degradation mechanisms. Further insight into ageing phenomena was gained using modelling -- showing how degradation in a typical LUT would be affected by different usage conditions, and predicting in detail the effects on circuit behaviour.