Variance reduction and outliers: statistical analysis of semiconductor test data
Variance reduction and outliers: statistical analysis of semiconductor test data
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方差减少和异常值：半导体测试数据的统计分析
DOI：
10.1109/test.2005.1583988
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
R. Madge
中科院分区：
文献类型：
--
作者：
W. R. Daasch;R. Madge
这是ITC 2005系列讲座中关于深亚微米半导体测试数据统计分析的三篇论文中的第一篇。本文的主题是方差缩减和方差缩减在离群点筛选中的重要性。大多数讨论的测试数据统计分析方法都是基于数据驱动模型构建的概念。为了获得显著的方差降低，这些统计模型的常用方法是在假设感兴趣的芯片是无缺陷的情况下评估测试响应的逐个芯片估计。晶圆空间图案的模型、单参数和多参数回归证明了该概念的多样性和潜力。在这样一个框架内，它表明，显着减少的方差参数分布可以得到相应的改善离群检测
This is the first of three papers on the statistical analysis of deep-submicron semiconductor test data for the ITC 2005 Lecture Series. The subject of this paper is variance reduction and the importance of variance reduction in outlier screening. Most of the test-data statistical analysis methods discussed are based on the concept of data driven model building. To obtain significant variance reduction, the common approach for these statistical models is to evaluate a die-by-die estimate of the test response, under the assumption that the die of interest is defect-free. Models of the wafer spatial patterns, single parameter and multi-parameter regressions demonstrate the variety and potential of the concept. Within such a framework, it is shown that significant reductions in the variance of parametric distributions can be obtained with a corresponding improvement in outlier detection