Power-Aware Testing and Test Strategies for Low Power Devices
Power-Aware Testing and Test Strategies for Low Power Devices
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DOI：
10.1109/date.2008.4484642
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发表时间：
2008-03
期刊：
影响因子：
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通讯作者：
D. Gizopoulos;K. Roy;P. Girard;N. Nicolici;X. Wen
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文献类型：
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作者：
D. Gizopoulos;K. Roy;P. Girard;N. Nicolici;X. Wen
管理电路和系统的功耗现在被认为是半导体行业最重要的挑战之一。如今，诸如动态电压缩放、时钟门控或功率门控技术等精细的功率管理策略被用于控制功能操作期间的功率耗散。这些策略的使用对制造测试具有各种影响，因此，功耗感知测试越来越成为低功耗器件的可测试设计和测试准备过程中的主要考虑因素。这本书探讨了现有的解决方案的功耗感知测试和设计测试的传统电路和系统，并调查测试策略和EDA解决方案测试低功耗器件。
Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.