STATIC RANDOM ACCESS MEMORY USING QUATERNARY D LATCH
STATIC RANDOM ACCESS MEMORY USING QUATERNARY D LATCH
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发表时间：
2010
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通讯作者：
Vasundara Patel;K. Gurumurthy;V. Sheshadri;Sivaram Krishnan
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作者：
Vasundara Patel;K. Gurumurthy;V. Sheshadri;Sivaram Krishnan
本文提出了一种用四值逻辑实现静态随机存取存储单元的方法。该静态RAM基于四进制D锁存器。当选择线被断言时，存储的数据被放置在单元的输出上。当SELECT和WRITE均被断言时，D锁存器打开，并存储新的数据位。这里使用的D锁存器是使用Nmax、Nmin和四值反相器电路构建的。设计了4×4存储阵列，并与4×4阵列的四值静态CMOS存储单元进行了比较。SPICE编码使用0.18微米CMOS工艺完成，设计验证通过HSPICE和COSMOSSCOPE概要工具完成。对电路的功耗和时延进行了分析。新设计显示，在180 nm处，与四值静态CMOS存储单元的4x4阵列相比，平均功耗提高了65.28%，比二进制4x4阵列提高了75%。
: In this paper, the implementation of a static random access memory cell using quaternary logic is presented. This static RAM is based on quaternary D latch. When the select line is asserted, the stored data is placed on the cell’s output. When both select and write are asserted the D latch is open and a new data bit is stored. The D latch used here is built using NMAX, NMIN and quaternary inverter circuits. A 4x4 memory array have also been designed and compared with 4x4 array of Quaternary Static CMOS memory Cell.. The spice coding is done using 0.18µm CMOS technology and verification of the design is done through HSPICE and COSMOSSCOPE Synopsis Tools. Power and delay of the circuit is analyzed. New design shows 65.28% of improvement in average power dissipation when compared to 4x4 array of Quaternary Static CMOS memory Cell and 75% improvement over binary 4X4 array at 180nm.