Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
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工作频率为 3.3-4.5 GHz 的异步互锁流水线 CMOS 电路
DOI：
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
Keith Jenkins
中科院分区：
文献类型：
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作者：
Stanley Schuster;William Reohr;Peter Cook;David Heidel;Michael Immediato;Keith Jenkins
随着微处理器的性能进入GHz甚至更高的范围，芯片性能、功耗、噪声和时钟同步正成为巨大的挑战。互锁流水线CMOS（IPCMOS）是一种异步时钟技术，有助于解决这些挑战。本文展示了一个典型的块（例如，块D）与其相互作用的所有块互锁。在正向方向上，专用有效信号模拟通过每个驱动块的最坏情况路径，从而确定数据何时可以锁存在典型块内。在相反方向上，确认信号指示数据已经被后续块接收，并且新数据可以在典型块内被处理。在这种互锁方法中，只有当有操作要执行时才生成本地时钟。
Chip performance, power, noise, and clock synchronization are becoming formidable challenges as microprocessor performance moves into the GHz regime and beyond. Interlocked pipelined CMOS (IPCMOS), an asynchronous clocking technique, helps address these challenges. This paper shows how a typical block (e.g., Block D) is interlocked with all the blocks with which it interacts. In the forward direction, dedicated Valid signals emulate the worst-case path through each driving block and thus determine when data can be latched within the typical block. In the reverse direction, Acknowledge signals indicate that data has been received by the subsequent blocks and that new data may be processed within the typical block. In this interlocked approach local clocks are generated only when there is an operation to perform.